Pipeline registers can be added to the traceback unit by specifying the number of traceback stages per pipeline register.
Design and Implementation of Viterbi Decoder Using VHDL
Setting the property value to 4 results in the insertion of a pipeline register for every four traceback units in the model, as illustrated in the following figure:. The TracebackStagesPerPipeline implementation parameter provides you a way of balancing the circuit performance based on system requirements. A smaller parameter value indicates the requirement to add more registers to increase the speed of the traceback circuit.
Increasing the number results in a lower usage of registers along with a decrease in the circuit speed. Instead of using registers, you can choose to use RAMs to save the survivor branch information. There are two major differences between the register-based and the RAM-based traceback architectures. Firstly , the register-based implementation combines the traceback and decode operations into one step and uses the best state found from the minimum operation as the decoding initial state. The RAM-based implementation traces back through one set of data to find the initial state to decode the previous set of data.
Secondly , the register-based implementation decodes one bit after a complete trackback; while the RAM-based implementation traces back through M samples, decodes the previous M bits in reverse order, and releases one bit in order at each clock cycle. Due to the differences in the two traceback algorithms, the RAM-based implementation produces different numerical results than the register-based traceback. A longer traceback depth, for example, 10 times of constraint length, is recommended in the RAM-based traceback to achieve a similar bit error rate BER as the register-based implementation.
The size of RAM required for the implementation depends on the trellis and the traceback depth. The following table summarizes the RAM usage for some typical trellis structures. The two implementations provide a register-RAM tradeoff that can be tailored to the individual design. Clark, G. Bibb Cain. Feygin and P. A modified version of this example exists on your system. Do you want to open this version instead?
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Pointers to them are added in this page on a regular basis. I recommend the following textbooks to learn more about the fascinating topic of error correcting codes:. Lin and D. Costello, Jr. Peterson and E. This modified algorithm is a key aspect of the Reed-Solomon decoder designs discussed in this thesis. The details of the design of both RS encoders and decoders are presented in detail.
A program written in a high level language was designed so as to generate the VHDL code that corresponds to the algorithms for encoding and decoding. The resulting area and speed metrics are presented for several designs of Reed-Solomon encoders and decoders. Repository Staff Only: item control page.
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